Sunday, September 30th

Tutorial I

Beyond Gaming: Programming the PLAYSTATION3 Cell Architecture for Cost-Effective Parallel Processing
Rodric Rabbah, IBM

Tutorial II

Compiling Code Accelerators for FPGAs
Walid Najjar, UC Riverside

Monday, October 1st - 10.30 - 12.00

1A: System-Level Design Methods for MPSoC
Session chair: Todor Stefanov
Session co-chair: Sungchan Kim

1. Simultaneous Synthesis of Buses, Data Mapping and Memory Allocation for MPSoC
   Brett H. Meyer, Donald E. Thomas
2. A Framework for Rapid System-level Exploration, Synthesis, and Programming of Multimedia MP-SoCs
   M. Thompson, H. Nikolov, T. Stefanov, A. D. Pimentel, C. Erbas, S. Polstra,
   E. Deprettere
3. Predictable Execution Adaptivity through Embedding Dynamic Reconfigurability into Static MPSoC Schedules
   Chengmo Yang, Alex Orailoglu

1B: Specification Language and Model Transformations to Support Synthesis and Design
Session chair: Robert P. Dick
Session co-chair: John Darringer

1. Synchronization after Design Refinements with Sensitive Delay Elements
   Tarvo Raudvere, Ingo Sander, Axel Jantsch
2. Embedded Software Development on top of Transaction-Level Models
   Wolfgang Klingauf, Robert Günzel, Christian Schröder
3. Pointer Re-coding for Creating Definitive MPSoC Models
   Pramod Chandraiah, Rainer Doemer

Monday, October 1st - 13.30 - 15.30

2A: Secure Embedded Systems
Session chair: Catherine Gebotys
Session co-chair: Fadi Kurdahi

1. Dynamic Security Domain Scaling on Symmetric Multiprocessors for Future High-End Embedded Systems
   Hiroaki  Inoue, Akihisa Ikeno, Tsuyoshi Abe, Junji Sakai, Masato Edahiro
2. Secure FPGA Circuits Using Controlled Placement and Routing
   Pengyuan Yu, Patrick Schaumont
3. A Smart Random Code Injection to mask Power Analysis Based Side Channel Attacks
   Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
4. Ensuring Secure Program Execution in Multiprocessor Embedded Systems: A Case Study
   Krutartha Patel, Sri Parameswaran, Seng Lin Shee

2B: Heterogeneous Computing Platform Simulation and Debug
Session chair: Franco Fummi
Session co-chair: Ahmed Jerraya

1. Combined Approach to System Level Performance Analysis of Embedded Systems
   Simon Künzli, Arne Hamann, Rolf Ernst, Lothar Thiele
2. Event-based Re-training of Statistical Contention Models for Heterogeneous Multiprocessors
   Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
3. HySim: A Fast Simulation Framework for Embedded Software Development
   Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
4. A Computational Reflection Mechanism to Support Platform Debugging in SystemC
   Bruno Albertini, Sandro Rigo, Guido Araujo, Cristiano Araujo, Edna Barros, Williams Azevedo

Monday, October 1st - 16.00 - 17.30

3A: Static and Dynamic Techniques for Partitioning and Scheduling
Session chair: Jianwen Zhu
Session co-chair: Paul Pop

1. Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems
   Pao-Ann Hsiung,  Chih-Wen Liu, Pin-Hsien Lu
2. Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators
   Greg Stitt, Frank Vahid
3. HW/SW Co-Design for Esterel Processing
   Sascha Gädtke, Claus Traulsen, Reinhard von Hanxleden

3B: Low Power Design and Thermal Control
Session chair: Joerg Henkel
Session co-chair: Naehyuck Chang

1. Power Deregulation: Eliminating Off-Chip Voltage Regulation Circuitry From Embedded Systems
   Seunghoon Kim, Robert P. Dick, Russ Joseph
2. Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization
   Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Giovanni De Micheli
3. Three-Dimensional Multiprocessor System-on-Chip Thermal Optimization
   Chong Sun, Li Shang, and Robert P. Dick

Monday, October 1st - 17.30 - 18.00

Break

Tuesday, October 2nd - 09.00 - 10.00

Keynote moderated by Jürgen Teich

1. Complexity Challenges towards 4th Generation Communication Solutions
   Hermann Eul, Infineon, Germany

Tuesday, October 2nd - 10.30 - 12.00

Special Session I: Fresh Air: The Emerging Landscape of Design for Networked Embedded Systems
Session Organizer: Radu Marculescu, Carnegie Mellon University

1. Networked embedded systems: How to ensure functional correctness in an unreliable, unpredictable, widely distributed environment
   Alberto Sangiovanni-Vincentelli, Dept. of EECS, Univ. of California, Berkeley, CA 94720
2. The future of spectrum utilization
   Borivoje Nikolic, Dept. of EECS, Univ. of California, Berkeley, CA 94720
3. Probabilistic approaches for communication-centric design at nanoscale
   Radu Marculescu, Dept. of ECE, Carnegie Mellon University,Pittsburgh, PA 15213

Tuesday, October 2nd - 13.30 - 15.30

4A: Embedded Software
Session chair: Joseph Buck
Session co-chair: Rolf Ernst

1. Locality Optimization in Wireless Applications
   Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala,, Arnout Vandecappelle
2. A Code-Generator Generator for Multi-Output Instructions
   Hanno Scharwaechter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Jonghee Youn, Yunheung Paek
3. Influence of Procedure Cloning on WCET Prediction
   Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel, Henrik Theiling
4. Compile-Time Decided Instruction Cache Locking Using Worst-Case Execution Paths
   Heiko Falk, Sascha Plazar, Henrik Theiling

4B: Advances in NoC Optimization
Session chair: Twan Basten
Session co-chair: Srinivasan Murali

1. Channel Trees: Reducing Latency by Sharing Time Slots in Time-Multiplexed Networks on Chip
   Andreas Hansson, Martijn Coenen, Kees Goossens
2. Performance and Resource Optimization of NoC Router Architecture for Master and Slave IP Cores
   Glenn Leary, Krishna Mehta, Karam S. Chatha
3. Incremental Run-time Application Mapping for Homogeneous NoCs with Multiple Voltage Levels
   Chen-Ling Chou, Radu Marculescu
4. A Data Protection Unit for NoC-based Architectures
   Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano

Tuesday, October 2nd - 16.00 - 17.30

5A: System-Level Performance Analysis
Session chair: Robert A. Walker
Session co-chair: Hiroyuki Tomiyama

1. Complex Task Activation Schemes in System Level Performance Analysis
   Wolfgang Haid, Lothar Thiele
2. Improved Response Time Analysis of Tasks Scheduled under Preemptive Round Robin
   Razvan Racu, Li Li, Rafik Henia, Arne Hamann, Rolf Ernst
3. Probabilistic Performance Risk Analysis at System-Level
   Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel

5B: Case Studies and Emerging Techniques
Session chair: Ahmed Jerraya
Session co-chair: Rainer Dorsch

1. ESL Design and HW/SW Co-verification of High-end Software Defined Radio Platforms
   A. C. H. Ng,, J. W. Weijers, M. Glassee, T. Schuster, B. Bougard, L. Van der Perre
2. Smart Driver for Power Reduction in Next Generation Bistable Electrophoretic Display Technology
   Michael A. Baker, Aviril Shrivastava, Karam S. Chatha
3. On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks
   Siddharth Garg, Diana Marculescu

Tuesday, October 2nd - 17.30 - 18.00

Break

Wednesday, October 3rd - 10.30 - 12.00

Special Session II: Practical Approaches to System-level Performance Analysis
Session Chair: Oliver Bringmann, FZI Institute

1. Performance Modeling for Early Analysis of Multi-Core Systems
   Reinaldo Bergamaschi, Indira Nair, Gero Dittmann, Hiren Patel, Geert Janssen, Nagu Dhanwada, Alper Buyuktosunoglu, Emrah Acer, Gi-Joon Nam, Guoling Han, Dorothy Kucar, Pradip Bose, and John Darringer,  IBM T. J. Watson Research Center, Yorktown Heights, NY
2. Bridging Gap between Simulation and Spreadsheet Study
   Antoine Perrin and Frank Ghenassia, ST Microelectronics, France
3. Performance Analysis and Design Space Exploration for High-End Biomedical Applications: Challenges and Solutions
   Iyad Al Khatib, Axel Jantsch, KTH, and Davide Bertozzi, Luca Benini, U. Bologna

Wednesday, October 3rd - 13.30 - 15.00

6A: System-Level Synthesis
Session chair: Christian Haubelt
Session co-chair: Donatella Sciuto

1. A Low Power VLIW Processor Generation Method by Means of Extracting Non-redundant Activation Conditions
   Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2. Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems
   Paul Pop, Kåre Harbo Poulsen, Viacheslav Izosimov, Petru Eles
3. Reliable Multiprocessor System-On-Chip Synthesis
   Changyun Zhu, Zhenyu Gu, Robert P. Dick, Li Shang

6B: Embedded Systems Architecture
Session chair: Wayne Wolf
Session co-chair: Bruce Jacob

1. Aggressive Snoop Reduction for Synchronized Producer-Consumer Communication in Energy-Efficient Embedded Multi-Processors
   Chenjie Yu, Peter Petrov
2. Predator: A Predictable SDRAM Memory Controller
   Benny Akesson, Kees Goossens, Markus Ringhofer
3. Performance Improvement of Block Based NAND Flash Translation Layer
   Siddharth Choudhuri, Tony Givargis

Wednesday, October 3rd - 16.00 - 17.30

Panel
Automotive Networks – Are New Busses and Gateways the Answer or Just Another Challenge?

Moderator: Rolf Ernst, Technische Universitaet Braunschweig, Germany

Panelists:

Gernot Spiegelberg, Siemens VDO Automotive AG, Germany;

Thomas Weber, DaimlerChrysler AG, Germany;

Hermann Kopetz, Technische Universität Wien, Austria;

Alberto Sangiovanni-Vincentelli, UC Berkeley, USA;

Marek Jersak, Symtavision GmbH, Germany