Tutorials
Hardware and Software Architectures for the CELL processor
Sunday, September 18, 2005, 9:00hs -- 12:00hs
Speakers
Peter Hofstee, Cell Chief Scientist and Cell Synergistic Processor Chief Architect, IBM Systems & Technology Group, Austin, Texas
Michael Day, Cell Chief Software Architect and Distinguished Engineer, IBM Systems & Technology Group, Austin, Texas
Abstract
The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3(TM)), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive applications. Cell addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms; a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low voltage. The Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting programmers and compilers explicit control over instruction scheduling, data movement and the use of a large register file.
Outline
- Cell goals and rationale
- Broadband Processor Architecture
- Cell processor overview, speeds and feeds
- Power core microarchitecture
- Synergistic processor microarchitecture
- System architecture and real-time aspects
- Programming models
- Prototype software stack
- Cell applications
Speakers' Bios
Michael Day graduated with a Bachelor of Science degree in Electrical Engineering - Computer Science block from the University of Texas at Austin in 1977. Michael joined IBM in 1977 as an engineer designing and implementing hardware and software for a large multi-user timesharing office product system including workstation controllers, full page displays, speech digitization and filing systems. He then became the lead firmware and software architecture for IBM's first battery powered laptop with advanced power management features. Michael moved to the IBM's premier Unix OS project called AIX in 1987 as kernel subsystem architect. Michael was voted into the IBM Academy of Technology in 1992, and went on to become chief architect of AIXv4 delivering SMP support and kernel based threads. He then lead a real-time broadband video streaming project, introducing the MediaStreamer product based on AIX in 1998. Michael was one of the first engineers to be appointed IBM Distinguished Engineer in 1997. He then went on to drive the design and implementation of AIX on IA64, then moved to the STI project in 2001 as Chief System Software Architect, defining the programming features of the Cell processor, enabling Linux and software tool chains to support various programming models for the Cell processor. Michael also leads a team of programmers developing application libraries, test suites, workloads and demonstration programs for the Cell processor. He is married to Karen Day and has two grown children, Troy and Paul.
Peter Hofstee received his doctorandus degree in theoretical physics from the Rijks Universiteit Groningen, The Netherlands, in 1988, and his M.S. and Ph.D. degrees in computer science from the California Institute of Technology in 1991 and 1994 respectively. After two years on the faculty at Caltech, he joined the IBM Austin Research Laboratory (ARL) in 1996. At the ARL he participated in the design of two 1GHz PowerPC prototypes, focusing on microarchitecture, logic design, and chip integration. In 2000 he helped start the Sony-Toshiba-IBM design center to design a next generation of processors for the broadband era, codenamed "Cell". Peter Hofstee is the chief scientist for Cell and the chief architect of the synergistic processor in Cell. Peter was elected into the IBM Academy of Technology in 2004.
Performance and Power Analysis of Computer Systems
Sunday, September 18, 2005, 14:00hs -- 17:00hs
Speaker
Prof. Trevor Mudge,
Bredt Family Professor of Engineering,
The University of Michigan, Ann Arbor
Abstract
This tutorial will present an overview of techniques for architectural-level performance and power analysis of computer systems. It starts with a discussion of metrics for both performance and power, followed by an overview of some widely used benchmarks including SPEC, Mediabench, and MiBench. It then illustrates the use of these benchmarks with some published performance results. After this initial overview, the tutorial will focus on a discussion of architectural
simulators to measure performance and power.
Architectural simulators model systems on a (clock) cycle-by-cycle basis. Their operation will be illustrated with two popular examples: SimpleScalar and M5. Besides performance analysis, these simulators can be extended to include power estimation. Full simulations of complete applications can be extremely time consuming. The tutorial will explain how sampling techniques can be used to reduce simulation time. Finally, it will conclude with a discussion on the accuracy that can be expected from architectural simulators.
Outline
- Introduction to architectural level performance and power analysis
- Metrics for performance and power
- Common benchmarks: SPEC, Mediabench. and MiBench
- Architectural simulators: SimpleScalar and M5
- Extension for power estimation
- Sampling techniques to reduce simulation time
- Limits to accuracy
Speaker's Bio
Trevor Mudge received a Ph.D. in Computer Science from the University of Illinois. Since then he has been at the University of Michigan. He was named the Bredt Professor of Engineering after a ten year term as Director of the Advanced Computer Architecture Laboratory, a group of a dozen faculty and 80 graduate students. He is author of numerous papers on computer architecture, programming languages, VLSI design, and computer vision. He has also chaired 33 theses in these research areas. He is a Fellow of the IEEE, a member of the ACM, the IEE, and the British Computer Society.
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